1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a symmetrical or asymmetrical transistor having an ultra short channel length dictated by the width of a gate conductor patterned upon a gate dielectric having a relatively high dielectric constant.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline silicon ("polysilicon") material over a relatively thin gate oxide arranged above a semiconductor substrate. The polysilicon material is patterned to form a gate conductor with source/drain regions (i.e., junctions) adjacent to and on opposite sides of the gate conductor within the substrate. The gate conductor and source/drain regions are then implanted with an impurity dopant. The gate conductor serves as a mask to an underlying channel region of the substrate during the implantation step. The implant energy is not sufficient enough to cause the dopant species to pass entirely through the gate conductor to the channel region. However, the implant energy is large enough to move the dopant species through the thin gate oxide to the underlying source/drain regions. If the dopant species employed for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (n-channel) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (p-channel) transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single monolithic substrate.
Because of the increased desire to build faster and more complex integrated circuits it has become necessary to reduce the transistor threshold voltage, V.sub.T. Several factors contribute to V.sub.T, one of which is the effective channel length ("Leff") of the transistor. The initial distance between the source-side junction and the drain-side junction of a transistor is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the junctions, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length. In VLSI designs, as the physical channel length decreases, so too must the Leff. Decreasing Leff reduces the distance between the depletion regions associated with the source and drain of a transistor. As a result, less gate charge is required to invert the channel of a transistor having a shorter Leff. Accordingly, reducing the physical channel length, and hence the Leff, can lead to a reduction in the threshold voltage of a transistor. Consequently, the switching speed of the logic gates of an integrated circuit employing transistors with reduced Leff is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies).
Unfortunately, minimizing the physical channel length of a transistor is somewhat limited by conventional techniques used to define the gate conductor of the transistor. As mentioned earlier, the gate conductor is typically formed from a polysilicon material. A technique known as lithography is used to pattern a photosensitive film (i.e., photoresist) above the polysilicon material. An optical image is transferred to the photoresist by projecting a form of radiation, typically ultraviolet light, through the transparent portions of a mask plate. The solubility of photoresist regions exposed to the radiation is altered by a photochemical reaction. The photoresist is washed with a solvent that preferentially removes resist areas of higher solubility. Those exposed portions of the polysilicon material not protected by photoresist are etched away, defining the geometric shape of a polysilicon gate conductor.
The lateral width (i.e., the distance between opposed sidewall surfaces) of the gate conductor which dictates the physical channel length of a transistor is thus defined by the lateral width of an overlying photoresist layer. The minimum lateral dimension that can be achieved for a patterned photoresist layer is unfortunately limited by, inter alia, the resolution of the optical system (i.e., aligner or printer) used to project the image onto the photoresist. The term "resolution" describes the ability of an optical system to distinguish closely spaced objects. Diffraction effects may undesirably occur as the radiation passes through slit-like transparent regions of the mask plate, scattering the radiation and therefore adversely affecting the resolution of the optical system. As such, the features patterned upon a masking plate may be skewed, enlarged, shortened, or otherwise incorrectly printed onto the photoresist.
Reducing the Leff of a transistor to below 1.0 .mu.m may lead to deleterious short channel effects ("SCE"). Generally speaking, SCE impacts device operation by, for example, increasing sub-threshold currents. A problem related to SCE and the subthreshold currents associated therewith, but altogether different, is the problem of hot-carrier effects ("HCE"). HCE is a phenomena by which the kinetic energy of the charge carriers (holes or electrons) is increased as the carriers are accelerated through large potential gradients and subsequently become trapped within the gate oxide. The greatest potential gradient, often referred to as the maximum electric field ("Em"), occurs near the drain during saturated operation of a transistor. More specifically, the electric field is predominant at the lateral junction of the drain adjacent the channel. As hot electrons travel to the drain, they lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs which migrate to and become injected within the gate dielectric near the drain junction. Vacancy and interstitial positions within the gate dielectric generally become electron traps, resulting in a net negative charge density within the gate dielectric. Unfortunately, the trapped charge may accumulate over time, causing the transistor threshold voltage to undesirably shift from its design specification. It is known that since hot electrons are more mobile than hot holes, HCE causes a greater threshold skew in NMOS transistors than PMOS transistors. Nonetheless, a PMOS transistor will undergo negative threshold skew if its Leff is less than, e.g., 0.8 .mu.m.
To overcome the problems related to HCE, an alternative drain structure known as the lightly doped drain ("LDD") has grown in popularity. The LDD structure advantageously absorbs some of the potential into the drain and thus reduces Em. A to conventional LDD structure is one in which a light concentration of dopant is self-aligned to the gate conductor followed by a heavier concentration of dopant self-aligned to the gate conductor on which two sidewall spacers have been formed. The purpose of the first implant dose is to produce a lightly doped section (i.e., an LDD area) at the gate edge immediately adjacent the channel. The second implant dose forms a heavily doped source/drain region spaced from the channel a distance dictated by the thickness of the sidewall spacer. A dopant gradient (i.e., graded junction) therefore results at the interface between the LDD area and the channel as well as between the LDD area and the source/drain region. The addition of an LDD implant adjacent the channel unfortunately adds capacitance and resistance to the source/drain pathway. This added resistance, generally known as parasitic resistance, can have many deleterious effects. For example, parasitic resistance can decrease the saturation drive current and the overall speed of the transistor. While it would seem beneficial to decrease both the drain-side parasitic resistance R.sub.D and the source-side parasitic resistance R.sub.S, the drain-side parasitic resistance is nonetheless needed to minimize HCE. Accordingly, proper LDD design must take into account the need for minimizing parasitic resistance at the source-side while at the same time attenuating Em at the drain-side of the channel.
It would therefore be desirable to develop a transistor fabrication technique in which the channel length of the transistor is reduced to provide for high frequency operation of an integrated circuit employing the transistor. More specifically, a process is needed in which the channel length is no longer dictated by the resolution of a lithography optical aligner, or dual sides of a masking structure. Thus, the Leff of a transistor must no longer be mandated by the lateral width of a lithographically patterned gate conductor. While minimizing Leff might afford high frequency operation of a transistor, it could also give rise to deleterious drain-side hot carrier injection into the gate dielectric. It would therefore be of benefit to develop an asymmetrical LDD design which serves to attenuate the maximum electric field Em in the critical drain area while reducing parasitic resistance R.sub.S in the source area. Such an LDD design would allow Leff to be reduced without being concerned that the transistor might experience problems associated with HCE and SCE as well as a reduction in saturation drive current.